The Seventeenth Asian Test Symposium
November 24-27, 2008, Keio Plaza Hotel Sapporo, Sapporo, JAPAN

News: Ealry Registration closes on Oct. 24th, 2008.

Keynote Speech & Invited Talk

Keynote Speech 1 (Nov. 25th, 9:20-9:45)

The Value of Extending Test Solutions

Presenter: Brian STEVENS (National Semiconductor - USA)

Summary:
In contemporary semiconductor product creation, de-compartmentalizing and applying previously operation-specific knowledge into different functional areas is valuable. This talk presents several examples of how test engineering expertise in an analog company was levered across functional area boundaries to help solve unique technical challenges and reduce overall new product cycle time. In this direction, the audience is urged to re-examine all processes related to semiconductor product development and further the trend of extending test innovation beyond traditional definitions and applications.

Keynote Speech 2 (Nov. 25th, 9:45 - 10:10)

Architectural Evolution and Test Requirements in Digital-Convergence Era

Presenter: Kunio UCHIYAMA (Hitachi - Japan)

Summary:
For digital systems in the digital-convergence era, various functions such as communication, security, audio, video, and recognition are required in a single device. However, improving the operating frequency of an embedded LSI in the system is saturated due to the significantly increasing power consumption problem. To solve this difficulty, the architecture of an LSI has been changing greatly these few years. This talk will review the recent architecture that targets a superior performance-per-power ratio and functional flexibility and the requirements to test the newly architected SoC. As the future mainstream direction, a parallelizing architecture that places multiple CPUs and special-purpose processors on a chip and that uses a parallelizing compiler will be discussed. Reviewing the low-power circuit and device technologies that support this multi-core architecture, test requirements will also be discussed.

Invited Talk 1 (Nov. 25th, 10:40-11:20)

The role of DFT in Yield

Presenter: Brady BENWARE (Mentor Graphics - USA)

Summary:
As technology nodes continue to scale, reaching mature yields in the same time as the previous node becomes increasingly difficult. In addition, mature yields are being eroded by design sensitivities to normal process variation. To combat these challenges, chip design is being called upon more than ever to help ensure designs are manufacturable and contain sufficient capabilities to determine the root cause of failures that arise in manufacturing. This presentation will first discuss the specific challenges in Yield Analysis and Failure Analysis that are resulting in slower yield ramps and lower mature yields. Secondly, a new approach to yield enhancement which effectively incorporates DFT technologies will be presented with silicon case studies that demonstrate specifically how DFT can contribute to solving yield problems in the nm era.

Invited Talk 2 (Nov. 25th, 11:20-12:00)

Issues and new Scenario for Deep sub-micron LSI design and Testing

Presenter: Kunihiro ASADA (University of Tokyo - Japan)

Summary:
The feature size of the LSI fabrication technologies is approaching to the extreme limit of the atomic size. Devices scaled down in LSI become more attractive in speed and power consumption, but less reliable and more variable in performance parameters. The reliability problem is caused by the miniaturized size and film thickness and some of variations in device parameters are physically intrinsic, caused by such as thermo-dynamic effects. One of the most important subjects in LSI design is to find a way to maximize the potential in performance with minimizing the essential weakness in device characteristics. In testing LSI, along with the conventional problems such as increasing complexity and decreasing observability/controllability, we will be faced with new issues of long term reliability and discrepancies between testing and real applications in terms of chip environments. We may have to give up the conventional scenario of the reliable pre-screening of defect-prone LSI by testing-before-shipping. In the presentation, after reviewing issues to be faced soon in LSI design and testing, a new scenario to overcome the issues will be proposed as a possible design and testing collaboration in the extremely deep sub-micron LSI era.

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